RC "Module" is the Russian leader in RISC and DSP Architectures and ASIC design is actively recruiting ASIC Design Engineers for exciting opportunities, based in Moscow, Russia.

Competitive salary and working conditions exist for:

Senior ASIC Designer (SAD)

Description
Conduct Synopsis synthesis, clock tree generation and control, Verilog coding and design logic, simulation, static timing checks, integration, verification, back-end support, testing and debugging for high-speed RISC and DSP projects.

Duties
Design high speed, low power digital functional blocks of CMOS ASICs for DSP and MCU at architectural and logic level. Will perform simulations using Verilog XL. Synthesize existing designs to optimize the timing and gate count. Work with back-end place and route engineers to provide timing constraints, perform back-annotation and validate timings (using Synopsys DC). Assist senior engineers in design verification at system and block levels. Work with product, test and application engineers in evaluating and debugging initial revisions of new silicon.
Requires individual with solid fundamentals of Verilog/VHDL design and synthesis and some experience with all aspects of design including power optimization, back-annotation of timing, test generation and system verification. Candidate must work with team, support groups and cross-divisional transfer of core technology.

Qualifications
Basic Experience: Two to three years in ASIC design. Experience in Synopsis synthesis and timing verification tools, Verilog block level design and chip level integration. Experience in control logic design as well high speed data manipulation logic.
Preferred Experience:
Three or more years with MCU and DSP ASIC design. Extensive knowledge of Synopsys and Cadence tools. Experienced in high speed mixed-signal design. The preferred candidate will have participated on a team, which has taken high-performance DSP from concept through complete chip debug.

Education
Basic:
MS in EE with emphasis on chip design.
Preferred:
MS in EE with emphasis on chip design and courses in DSP theory.

Citizenship: Russian

Please send your resume to employment@module.ru, preferably in ASCII or RTF format, and refer to SAD in the subject line of the email.