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MC405 Mezzanine Color VideoGrabber with
RS232 & RS485 controller
Scope
This document describes the Color VideoGrabber MC405 from User's perspective.
The MC405 is a mezzanine module predestined to be used together with
the NM4 DSP board. The MC405 consists of one SAA7110A multi-standard video
decoder by Philips Semiconductors with 0.5 Mbyte SRAM and RS232/RS485
controller based on Z85C30 chip by Zilog.
The module is typically suitable for the following applications:
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Image processing;
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Video Picture Grabbing;
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Multimedia;
Technical description
Fig.1 MC405 Block diagram Fig.1 shows the MC405 block diagram. The following section describes
MC405 from the user's point of view. Reference is made to the different
blocks in Fig.1.
Video Decoder
The one chip front-end SAA7110A is a digital multi-standard color decoder
(OCF1) on the basis of DIG-TV2 system with two integrated Analog-to-Digital
Converters (ADCs), a Clock Generation Circuit (CGC) and Brightness Contrast
Saturation (BCS) control.
Features:
- Two 8-bit video CMOS analog-to-digital converters
- Fully programmable static gain for the main channels or automatic
gain control for the selected CVBS/Y channel
- Selectable white peak control signal
- Luminance and chrominance signal processing for PAL B/G, NTSC and
SECAM
- Automatic detection of 50/60 Hz frame frequency, and automatic switching
between standards PAL and NTSC, SECAM
- Square pixel format with 768/640 active samples per line on the YUV-bus
- 4 : 2 : 2 YUV output formats with 8-bit resolution
- User programmable luminance peaking for aperture correction
- I2C-bus controlled.
SRAM
The SRAM is suitable for storage of digitized video frames and accessible
to read from NM4 board 0 processor. 512Kbyte SRAM bank is organized in
64K words by 64 bits. The SRAM accessible to write through window 5800C000
- 5800FFFF. Three most significant address bits stored at D2-D0 at 5800000E
register.
| Address |
Resource |
Comment |
| 50000000 - 50007FFF |
SRAM bank0 |
for
digitized frames.
may be united into big frames |
| 50008000 - 5000FFFF |
SRAM bank1 |
| 50010000 - 50017FFF |
SRAM bank2 |
| 50018000 - 5001FFFF |
SRAM bank3 |
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RS232/RS485 Controller
The Z85C30 SCC is a Zilog Serial Communications Controller. It is a dual
channel, multi-protocol data communications peripheral. Programming flexibility
of the internal registers allows the SCC to be configured to satisfy a
wide variety of serial communications applications. 5801Ñ000h corresponds
to B_contr register, 5801Ñ010h corresponds to B_data register, 5801Ñ020h
corresponds to A_contr register, 5801Ñ030h corresponds to A_data register.
RS485 port works as output when RTSB is active and as input when DTRB
is active. Interrupt from controller is connected to IIOF1 on NM4 board.
When RS485 works point-to-point, insert a jumper on X8 3-4 position (RTin).
When RS485 works in a multi-user mode, insert a jumper both on X8 3-4
and 5-6 position (RTout and RTin) for devices on the ends of chain but
you do not need a jumper for devices in the middle of the chain.
Jumper in X8 1-2 position connects CTSA signal for RS232 port.
Control Registers
Control Registers (CR) controls the mode and parameters of video-grabbing.
CR0 (58000000h) is a counter for I2C. Writing the number of bytes of Initialization
file causes transmission of this file to SAA7110A. The number of bytes
should be not more than 6 bit long. Reading this register shows the number
of unsent bytes. Transmission is complete when CR0 is equal to zero. The
initialization file must be placed on 5800FF00h in advance.
CR1 (580000004h) is a video-grabbing mode.
| bit |
=1 |
=0 |
| 0 |
all pixels in line |
only even pixels |
| 1 |
two half-frames |
one half-frame |
| 2 |
color |
monochrome |
| 3 |
4 bank SRAM used
for small frames |
2 bank SRAM used
for small frames |
| 4 |
WatchDog timer on
(only read) |
WatchDog timer off
(only read) |
| 5-7 |
reserved |
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Note: after reset all bits are equal
to zero.
CR2 (58000006h) are ready flags. Writing 1 in 0bit starts video-grabbing.
Writing 0 in the 0-th bit stops video-grabbing. Writing 1 in the 1-st
bit starts grabbing one frame. Reading CR2 shows ready flags in the 0-3-rd
bits. When a frame is placed in the SRAM bank, the corresponding flag
is set. The 4-th bit is set to one when video-grabbing is on. The 5-th
bit is set to one when a I2C error occurred.
CR3 (58000002h) is a watchdog timer mode. Writing 3Ch starts the timer,
writing C3h stops the timer, writing A5h resets the timer. When the watchdog
timer is on without resetting every 1/25s, the timer causes UPR1 interrupt
in NM4 board. After that 1/25s the timer causes system reset.
Interfaces
Three connectors X1, X2 and X3 (see fig.2) carry all the signals the
module requires to function. Refer to the NM4 Specification for the full
pinout description of the connectors.
Specification
The following important specifications should be noted when using the
MC405:
Table 2. MC405 Specifications
| Feature |
MC405 |
Units |
| Number of pixels |
768
x 576 or 384 x 288 |
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| Number of bit per
pixel |
8 |
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| Memory - SRAM |
0.5 |
Mbyte |
| Length |
160 |
mm |
| Width |
95 |
mm |
| PCB thickness |
1.6 |
mm |
| Operating temperature |
0
- 40 |
*C |
| Power supply voltage
VCC |
2.97
- 3.63 |
V |
| Power supply voltage
VDD |
4.5
- 5.5 |
V |
| Power consumption,
max |
2 |
W |
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Precautions
In order to guarantee that the MC405 functions are correct and to protect
the MC405 from damage, the following precautions should be taken: the
MC405 is a static sensitive device and should be handled accordingly.
Always place the MC405 in a static protective bag during storage and transition.
Power supply
The MC405 requires +5V, +3.3V for operation.
+5V and +3.3V is derived from NM4 through the X1, X2 and X3 connectors.
Documentation
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