RC "Module" has a many years of experience in digital and mixed-signal ASIC design and a solid track record of success with the leading semiconductor companies, including Samsung and Fujitsu.

RC "Module" uses a layout-driven bit-sliced approach to ASIC design and complexity management, and has successfully designed high-performance ASICs, such as the NeuroMatrix® NM6403 DSP and DSM SoC.

The design process typically starts with one or more customer meetings to determine and specify the exact customer requirements for the chip. RC "Module" prefers to become involved early in the customer's design process as RC "Module" engineers can often assist with determining the most efficient system partitioning and help the customer decide on the final feature set. Once the requirements for the chip are finalized, the implementation can commence.

RC "Module" uses Verilog as its high-level design language. The design is developed at the Register Transfer Level (RTL), with well-defined interfaces between the major blocks. Timing and testability issues are considered up front to avoid problems later in the design flow.

The design is verified using two sets of test suites: "hardware tests" and "software tests". The hardware test allows RC "Module" to achieve a high level of "fault coverage", while the second test predicts the behavior of the chip at a system level.

RC "Module" utilizes Synopsys Design Compiler and Fujitsu FAME5 layout tools, and again uses bit-slice methodologies and automated scripting to efficiently synthesize the design to meet timing constraints with the minimum chip area. Synopsys is also used for static timing analysis.

The tests are re-run at gate-level with estimated timing delays using the same verification environment as was used at the RTL level, ensuring that the synthesis produced accurate results.

The verified design is released for layout at first sign-off. The chip is laid out by the vendor, who returns the post-layout netlist with final timing information. The same hardware and software tests are re-run again to ensure that no timing problems were introduced during routing, and that the final design will function in the system. The final verified design is signed off for the second time for wafer fabrication.

RC "Module" offers post-silicon support in the form of system validation and thorough checkout of the chip in its system environment.

RC "Module" is a hotbed of innovation. The company has patented Silicon Intellectual Property (SIP) for high-performance RISC and DSP architectures The NeuroMatrix^® Core is available for licensing now.