1879BA1T MIL-STD-1553B Interface Terminal

• Documentation

1879BA1T interface terminal provides complete, flexible interface between host processor and MIL-STD-1553B redundant data bus via external transceivers, implementing Bus Controller (BC), Remote Terminal (RT), Monitor Terminal (MT) or simultaneous RT/MT modes.

Description:

1879BA1T integrate encoder/decoder, complete BC/RT/MT multi-protocol logic, interrupt logic, control logic, memory management and processor interface logic, and 4K words of internal buffered SRAM. 1879BA1T may use up to 64K words of external SRAM at DMA configuration. 1879BA1T may be interfaced both to 16-bit and 8-bit microprocessors at shared memory mode. 1879BA1T runs at either 16 or 12 MHz software programmable clock rate.

1879BA1T BC and RT protocols implements all MIL-STD-1553B message formats, providing flexible interface to CPU and many advanced features. 1879BA1T implement three MT modes: word monitor, selective message monitor, simultaneous RT/message monitor, with trigger options.

1879BA1T require only single +3.3V power supply, provide CMOS output levels and have 5V-tolerant inputs. 1879BA1T comply with both Harris-compatible and Smiths-compatible MIL-STD-1553B data bus transceivers. 1879BA1T packaged at 14 x 14 mm 80-pin plastic LQFP with 0.5 mm pitch and have maximum height 1.7 mm that is well suited for applications with stringent height requirements.

Designed by RC MODULE devices 1553 terminals with 1879BA1T and various models of data bus transceivers were fully tested to compliance with MIL-STD-1553B requirements at S.P.Korolev RSC ENERGIA test house.

Features:

• Complete integrated interface between host processor and MIL-STD-1553B data bus via external transceivers
• BC, RT, MT, simultaneous RT/MT modes
• 4Kx16 internal RAM, externally expanded to 64Kx16
• Flexible processor/memory interface:
• 8- or 16-bit buffered mode
• 16-bit transparent mode
• 16-bit DMA mode
• supports "Zero Wait" mode
• 16/12 MHz programmable clock rate
• Advanced BC features:
• automatic retries
• programmable gap times
• frame auto-repeat
• programmable response time-out
• Advanced RT features:
• programmable illegalization
• choice of single message mode, double buffering mode, and circular buffering mode
• interrupts on individual mode codes
• flexible data buffering
• Advanced MT features:
• word monitor mode
• selective message monitor mode
• simultaneous RT/message monitor mode
• trigger options
• Single +3.3V power supply, 5V-tolerant inputs
• 14 x 14 mm 80-pin LQFP package

Fig.1. Functional Diagram

Applications:

Interfacing of host processors to MIL-STD-1553B redundant data bus at avionics and other mission-critical applications, development of hardware and software test systems

Specifications:

Documentation

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